Flash memory is used in a variety of computer applications. For parallel types of flash memory, the signal interface between a computer processor and an external flash memory is controlled as specified by the external flash manufacturer. Some manufactures provide mechanisms via this interface to prevent or help recover from the effects of corruption of flash memory contents, such as that which can occur when the power supply to the computer processor and/or flash memory is interrupted. However, serial types of flash memory have become more popular and do not typically include such mechanisms.
This can present a problem in systems having external serial flash memories coupled to host processors, in which the power to the system can be removed at any time. This requirement is especially challenging if the external flash memory is being erased or programmed by the host processor when power is removed.
Co-pending U.S. application Ser. No. 14/554,325, the contents of which are incorporated herein by reference in their entirety, dramatically advanced the state of the art by providing methods and apparatuses in which non-volatile RAM in the system is used to log write and erase operations to external serial flash memory. This log information is used to determine if a sector should be erased on power up because power was removed while a program or erase operation was occurring. However, in some systems, backup power may not be maintained to the non-volatile RAM while power is removed. Consequently, the non-volatile RAM may be invalid when power is reapplied, such that all sectors in external serial flash memory that could be in a partially programmed or over-erased state are erased. Accordingly, there remains a need for a solution to this problem, among others.